1. Field of the Invention
Embodiments of the present invention generally relate to the fabrication of integrated circuits and particularly to planarizing etch hardmask processes for obtaining an increased aspect ratio feature in a desired film stacks or increasing the pattern density for a given region.
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors and resistors on a single chip. The evolution of chip design continually requires faster circuitry and greater circuit density. The demand for faster circuits with greater circuit densities imposes corresponding demands on the materials used to fabricate such integrated circuits.
Hardmasks are being used for almost every step in integrated circuit manufacturing processes for both front-end and back-end processes. As device sizes shrink and pattern structure becomes more complex and difficult to manufacture, an etch hardmask is becoming more important as photoresists currently available are failing to meet the etching resistance requirements and photoresists are simply being used for image transfer rather than as an etch mask in a lithography and etching process. Instead hardmasks that receive the image pattern are becoming the primary material for effective etching of patterns in underlying layers.
Amorphous hydrogenated carbon is a material that may be used as a hardmask for metals, amorphous silicon, and dielectric materials, such as silicon dioxide or silicon nitride materials, among others. Amorphous hydrogenated carbon, also referred to as amorphous carbon, is typically used as an etch hardmask in semiconductor applications due to its high chemical inertness, optical transparency, and easy removal. The continued reduction in device geometries has generated a demand for methods of forming nanometer scale features that are separated by nanometer scale distances on semiconductor substrates. However, as the minimum feature size decreases, the semiconductor industry is facing the limitation of patterning sub-32 nm due to the limits of optical resolution being approached in current lithography processes. Meanwhile, there has always been a great demand for a device with an increased circuit density and/or high aspect ratio structures in order to achieve higher device performance.
Therefore, there is a need for improved patterning processes which are capable of increasing the pattern density for a given region or obtaining an increased aspect ratio feature in a desired film stacks for semiconductor applications.